FPGA Based Digital World - FPGA Technology

FPGA Technology

When you're asked to design a circuit to realize below 2-bit decoder,

you must be very happy, 'cause it's quite simple - a standard logic IC 74xx139 is capable of doing this easily.

When the job is done, your boss suddenly changes his mind and asks you to add more such decoders, and other logics. Your design would look like this.

That's not the end - the user finds that it's not the one he wants, then you need to redesign it.

In this case, why not consider using a monolithic PLD(e.g. FPGA, CPLD,etc.) ? Let's take a look at FPGA then.

A FPGA(Field Programmable Gate Arrays) is a completely reprogrammable semiconductor device to desired application or requirements after manufacturing.Introduced by Xilinx in 1985, XC2064 was the first commercial FPGA.Till now, FPGA has become more and more flexible and larger, and has been applied in many areas,e.g., imgage processing, realtime control,machine learning,wireless communication, etc..

A FPGA is based on a matrix of configurable logic blocks(CLBs) or logic array blocks(LABs) connected by programmable interconnects, and generally consists of below basic components:

- Configurable CLB(Configurable Logic Block) or LAB(Logic Array Block);

- Programmable interconnects;

- Configurable I/O Blocks;

- Clock Managment Blocks;

- Other Resources, e.g., DSP, RAM, etc.

Below is a generic FPGA structure[11].

The structure of Altera(Intel) Stratix as an FPGA example is shown below[7][8].

In Stratix, each LAB consists of 10 LEs(or ALM-Adaptive Logic Module from Stratix II on), LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines, as below.

And LE(Logic Element) or ALM(Adaptive Logic Module) is the smallest unit in a Stratix architecture, configurable to combinational or sequential logic, shown below.

In addition, via configurable I/O block, each I/O can be congifured to differetial or single-ended types with different voltages(e.g., 3.3V, 2.5V, 1.8V,etc.).

With the FPGA, you can implement your design via different configuration from programming languages, e.g., VHDL, Verilog HDL, C, etc.

A simple VHDL example to realize n 2-bit encoders is listed here.

-- Example of VHDL for Encoders
-- Copyright by fpgadig.org

-- Libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Declaration of the component
ENTITY EncodersExample IS

GENERIC
(
ENC_COUNT : natural := 2 -- Parameter: encoder number
);

PORT
(
reset_H : in std_logic;
a_data_in_H : in std_logic_vector(ENC_COUNT*2-1 downto 0);
q_data_out_H: out std_logic_vector(ENC_COUNT*4-1 downto 0)
);

END entity;

-- Impelmentation of the component
ARCHITECTURE rtl OF EncodersExample IS
-- Function to realize one 2-bit encoder
procedure Encoder2Bit( signal data_in_H : in std_logic_vector(1 downto 0);
signal data_out_H : out std_logic_vector(3 downto 0)
) is
begin
case data_in_H is
when "00" => data_out_H <= "0001";
when "01" => data_out_H <= "0010";
when "10" => data_out_H <= "0100";
when "11" => data_out_H <= "1000";
when others => data_out_H <= (others=>'Z');
end case;
end;
BEGIN

process (reset_H,a_data_in_H)
variable i: integer :=0;
begin

if ( '1' = reset_H )then
-- Reset the outputs to high impedance States
q_data_out_H <= (others=>'Z');

else
-- Setup all outputs accordingly
for i in 1 to ENC_COUNT loop
Encoder2Bit( a_data_in_H(i*2-1 downto i*2-2),q_data_out_H(i*4-1 downto i*4-4) );
end loop;
end if;
end process;

END rtl;

To make the above code work in a FPGA, you need to do below tasks(tiring, right? ).

The above topics will be dicussed in details in the correponding parts of this website.

The FPGA design methodology is not as mature as software developement(e.g., software engineering, design pattern, architecture pattern, etc.). As a matter of fact, dataflow diagram(DFD) is one of my favorite tool to design a new project, not only for structured design of embedded software, but also for FPGA developement. It helps you from the concept phase to the design phase, more and more detailed.

The sythesized RTL model and the resource used in the FPGA for the above encoder can be seen below.

If the requirement of the user is changed, you just need to modify the VHDL code and do the tasks again without adding new chips(if only the logic function is touched).So, it's quite flexible.

The two main vendors in the FPGA market are Altera(Intel) and Xilinx(AMD), and below is the market share in 1998(EE Times, 1999)

And in 2018, the market share becomes[12].

Programmable Devices in Artifical Intelligence(AI)

The field-programmable concept has been spread to some specific areas, e.g., AI.

Below is the concept of Field-Programmable Learning Array[9].

And below is the concept of Field Programmable Deep Neural Network (DNN) Learning & Inference accelerator[10].

FPGA vs. MCU(MicroController Unit)

In fact, the flexible logic could also be implemented by a MPU in a different way.

Logic Circuit: from Discrete Digital Component to PLD, and to SoC

Suppose we're gonna design a circuit to realize below logic function

X = AB+CDE+FGH

let's find the possible ways to impement it.

The first idea may be to realize it with discrete compoents with AND and OR gates, as shown below.

As it can be seen, too many components are employed in the circuit.

Is there a way to combine them into one monolithic chip? Yes, that's the SSI(small scale integration) general purpose logic ICs(e.g., 74 series, 4000 series, etc.).

A SN74H62 is capable of implementing the above circuit in a monolithic chip.

If the above general purpose IC fails to meet your need, you can design and manufacutre your own ASIC(Application-Specific Integrated Circuit) to embed all the logic circuits into a monolithic chip. An ASIC has higher performance and increased densities, yet it lacks flexibility for changes and difficult to be tested or debug.

In addition, ASIC is much expensive if the quantity of ASIC mass production is small, so it's not suitable for small batch product. In this case, PLD(programmable logic device) is a better choice - a PLD can be programmed in the field after its production to realize different functions according to the need.

As you know, any combinational logic function can be expressed in two ways:

- combination of basic logic gates( e.g., OR, AND, etc.);

- truth table

To realize a sequential logic, DFF(D-type Flipflop) or latch can be connected between the combinational logic.

And that's the basis of PLD accordingly.

- Combine PROGRAMMABLE OR gates array and/or AND gates array together to realize the target logic: PLA, PAL or GAL

- Use programmable LUT(Lookup table) to realize the target logic: PROM

The PLD can be divided into several types according to its structure and compexicity.

Till now, CPLD and FPGA are still in fashion, while PROM,PLA, PAL and GAL as programmable logic circuits have become out of date.

PROM, PLA, PAL and GAL were the PLDs employing combined OR and/or AND gates to be programmable(PROM can also be viewed as programmable LUT).

1) PROM(Programmable Read-only Memory)

PROM was the earlier PLD in the early-1970s, capable of implementing programmable LUT, with its address pins as input and data pins as output.

From another point of view, PROM is a PLD with fixed AND array( connected to address) and programmable OR array( connected to the data pins).

The structure of 82S126 as a PROM example is shown below.

Limited by its structure, PROM can only realize simple combinational logic.

2) FPLA(Field Programmable Logic Array)

FPLA was the follow on of PROM, introduced in the mid-1970s. The FPLA consists of programmable AND arrays and OR arrays.

The structure of a FPLA example(82S100) is shown below.

The FPLA was slow and difficult to use, so it was less profili and didn't gain great success comparing with its followers - PAL and GAL. Yet, it built the base of its followed PLDs.

3) PAL(Programmabl Array Logic)

In the late-1970s, PAL consisting of programmable AND arrays and fixed OR arrays was introduced by MMI(Monolithic Memories). Comparing with FPLA, it's more readily availalable with easy production, due to its simpler structure(OR arrays are fixed). And it works faster than FPLA although its flexibility is less.

Below is the structure of PAL20L2 as an example.

In a PAL,

-The AND plane provides the connections between the inputs and the AND gates or the product terms that implement the logic functions or control logic;

-The OR-plane makes the connections between the AND-plane and the outputs;

-The flip-flops(D-type, J-K, R-S or T-type) or latch provide clocking or feedback into the logic, determining the output to be configured as sequential or combinatorial logic;

4) GAL(Generic Array Logic)

PAL devics are OTP(One-time programmable) chips. So in 1985, electrically erasable and programmable GAL based on EEPROM technology was introduced by Lattice Semiconductor. It was almost 100% compatible with PAL and able to emulate a wide variety of PAL, so GAL devices are direct replacement of most PALs.

Similar to PAL, a GAL consists of programmable AND array and fixed(or programmable) OR array. Besides, it includes programmable OLMCs(Output Logic Macrocell) to support sequential logic with a DFF inside each OLMC, as well as to support different I/O types.

As an example, the structure of GAL20V8 is shown below.

Checking the above ealier SPLDs(simple programmable logic device, e.g., PROM, PLA, PAL and GA, etc.), you could find that the flexible logic AND or OR array relies on the programmable connections between the them, as shown in below abstract of the SPLD.

Due to the limit function of AND and OR gates, the SPLD are only capable of constructing small-scale logic.

If we try to

- expend the single-functional OR and AND gate to programmable complex logic block(PCLB), e.g., a SPLD, a LUT, a SRAM, a DSP, etc.

- add programmable I/O element for the input and output

The PLD would be more flexible and powerful-that's CPLD and FPGA that we're gonna talk about. Below is the abstract structure of CPLD and FPGA.

5) FPGA

The fisrt commercial FPGA - XC2064 was introduced by Xilinx in 1985, and can be found in the IEEE chip hall of fame[1].

Below is the structure of XC2064,and a detailed structure of this early FPGA can be found in [2].

It's fully field-programmable

- I/O functions: I/O block

- Digital logic functions: CLB(configurable logic block) is the core block to realize the logic functions with LUT, implemented with multipexers.

- Interconnections

Modern FPGAs are more flexible and with abundant resources like DSP, PCIe, SRIO, etc.

6) CPLD

In 1988, altera(now merged to Intel) introduced the first CPLD(Complex Programmable Logic Device) - MAX5000, consisting of PAL-Type blocks with connections between them.

The structure of the early Max5000 CPLD is shown below.

Below is the similar structure of Xilinx(now merged to AMD) CPLD - CoolRunner II[4].

In this CPLD, the Function Block(FB) is the main configurable block to implement the target logic, and all the FBs are connected to the programmable AIM(Advanced Interconnect Matrix).

- Function Block(FB)

Each FB contains 16 macrocells, with 40 entry sites for signals to arrive for logic creattion and connection, and the internal logic engine is a 56 product term PLA.

Below is the structure of a macrocell.

- Advanced Interconnect Matrix (AIM)

The AIM is programmable, and results from all FB macrocells, as well as all pin inputs circulate back through the AIM for additional connection available to all other FBs as dictated by the design

- I/O Block

Each I/O is either automatically compliant with standard voltage ranges or can be programmed so via the I/O block.

The logic blocks of the above CPLDs are based on PAL or the combination of basic logic gates of AND and OR, XOR, NOR, etc.. In addition, the logic blocks or function blocks are connected to the same connection matrix(AIM or PIA).

As a specical case, the structure of the Altera(Intel) MAX V CPLD is a different[5].Its logic block is LUT - the same as in FPGA, as shown below.

and it uses Multitrack interconnect which comprises of row&column interconnects, yet still keeps continous interconnect and uinform length, as shown below.

Despite of the above difference, it keeps the same characteristics of a CPLD.

CPLD and FPGA are used in different senerios due to their differences: CPLD is proper for fast-speed and simple project, and FPGA is useful in complex projects. And sometimes they're combined in a circuit: CPLD is used to configure the FPGA during FPGA startup.

Below are some differences between CPLD and FPGA.

- Flexibility

The FPGA has finer granule than CPLD.

In addition, the resources are limited in a CPLD due to its fabric scheme, while with FPGA, many additional hardware components are available, e.g., DSP, tranceivers, RAM, etc..

So FPGA is more flexible.

- Performance Predictability

In a CPLD, the interconnect between different logic cells are central or continous, so the contant delay between two logic cells are predictable. While in a FPGA, the interconnect is segmented and the interconnect delay is directly porportional to the number of segments necessary to route a signal and it's impossible to know this number[5].

- Logic Resources

The number of logic resources(<500FFs) in a CPLD is relative smaller than a FPGA.

So a CPLD is suitable for 'glue logic' functions(esp. combinational logic) while FPGA is suitable for sequential logic.

- Power On Speed

The programming technologies used in CPLD are usually EPROM, EEPROM, FLASH (sometimes SRAM), so the CPLD is usaually non-volatile and instantly powered on.

While in FPGA, SRAM CMOS programming technologies are mostly used(sometimes anti-fuse or FLASH). So a FPGA needs some time to load the configuration from external ROM and takes longer time to power up.

With the need of more and more complex computations, a MPU or MCU is usually integrated into a FPGA, forming a SoC.

References

[1] Chip Hall of Fame: Xilinx XC2064 FPGA, https://spectrum.ieee.org/tech-history/silicon-revolution/chip-hall-of-fame-xilinx-xc2064-fpga

[2] Reverse-engineering the first FPGA chip, the XC2064, http://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html

[3] Max5000 Programmable Logic Device Family Datasheet, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/archives/m5000.pdf

[4] Xilinx CoolRunner-II CPLD Family Datasheet,https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

[5] MAX V Device Handbook,https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf

[6] CPLDs vs. FPGAs Comparing High-Capacity Programmable Logic, Altera(Intel) Company

[7] The Stratix II Logic and Routing Architecture, Altera(Intel) Company

[8] Stratix Device Handbook, Altera(Intel) Company

[9] Seth Bridges, Miguel Figueroa, David Hsu, and Chris Diorio, Field-Programmable Learning Arrays

[10] LUIZ M FRANCA NETO, Field Programmable Deep Neural Network (DNN) Learning & Inference accelerator: a concept

[11] Eric Monmasson, Marcian Cirstea,FPGA Design Methodology for Industrial Control Systems – a Review , IEEE

[12] Owais Ahmed, Latest FPGAs in the market, 2018


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